1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device including a delay locked loop (DLL) and a method for driving the same.
2. Description of the Related Art
With the increase of integration degree, the semiconductor device has improved to increase the operation speed. To increase the operation speed, a synchronous memory device capable of operating in synchronization with an external clock signal, which is applied from outside, has emerged. The synchronous memory device includes a DLL to output data in synchronization with rising and falling edges of the external clock signal. The DLL compensates for a delay factor occurring in an internal circuit of the semiconductor memory device and generates an internal clock signal in response to the external clock signal. At this time, a state after when the internal dock signal is completely generated refers to locking.
FIG. 1 is a block diagram of a conventional semiconductor device.
Referring to FIG. 1, the semiconductor device 100 includes an input buffer 110, a DLL 120, a transmission line 130, and an output buffer 140. The input buffer 110 is configured to buffer an external clock signal EXTCLK and generate a reference clock signal REFCLK. The DLL 120 is configured to generate a DLL clock signal DLLCLK corresponding to the reference clock signal REFCLK. The transmission line 130 is configured to transmit the DLL clock signal DLLCLK. The output buffer 140 is configured to receive input data INT_DATA to output data DQ_DATA to the outside in response to the DLL clock signal DLLCLK, which is transmitted through the transmission line 130.
FIG. 2 is an internal configuration diagram of the DLL 120 illustrated in FIG. 1.
Referring to FIG. 2, the DLL 120 includes a variable delay unit 121, a replica delay unit 123, a phase comparison unit 125, and a delay control unit 127. The variable delay unit 121 is configured to generate the DLL clock signal DLLCLK by delaying the reference clock signal REFCLK by a first delay amount, which is required for locking in response to a delay control signal DLY_CTRL<0:n>. The replica delay unit 123 is configured to generate a feedback clock signal FDBCLK by delaying the DLL clock signal DLLCLK by a second delay amount occurring in an internal input or output path that includes the input buffer 110, the transmission line 130, and the output buffer 140. The phase comparison unit 125 is configured to compare a phase of the feedback clock signal FDBCLK to a phase of the reference clock signal REFCLK and generate a phase comparison signal PD based on the comparison result. The delay control unit 127 is configured to generate the delay control signal DLY_CTRL<0:n> in response to the phase comparison signal PD and an initial setting signal RESET.
Here, the variable delay unit 121 tracks the first delay amount based on a preset initial delay amount in response to the initial setting signal RESET and the delay control signal DLY_CTRL<0:n>.
The replica delay unit 123 reflects a delay amount obtained by modeling the internal input or output path into the DLL clock signal DLLCLK, and outputs the feedback clock signal FDBCLK.
The phase comparison unit 125 detects a phase difference between the feedback clock signal FDBCLK and the reference clock signal REFCLK, and outputs the phase comparison signal PD corresponding to the detection result.
The delay control unit 127 outputs the delay control signal DLY_CTRL<0:n> corresponding to a delay amount to be controlled in response to the phase comparison signal PD.
Hereafter, an operation of the semiconductor device 100 having the above-described configuration will be described with reference to FIG. 3.
FIG. 3 is a timing diagram for explaining the operation of the conventional semiconductor device 100.
Referring to FIG. 3, the input buffer 110 buffers the external clock signal EXTCLK and generates the reference clock signal REFCLK. Furthermore, the DLL 120 generates the DLL clock signal DLLCLK corresponding to the reference clock signal REFCLK. The detailed operation of the DLL 120 is performed as follows.
The variable delay unit 121 delays the reference clock signal REFCLK by the initial delay amount in response the initial setting signal RESET and outputs the DLL clock signal DLLCKL. The replica delay unit 123 delays the DLL clock signal DLLCLK by the second delay amount occurring in the internal input or output path and outputs the feedback clock signal FDBCLK. The phase comparison unit 125 compares the phase of the reference clock signal REFCLK to the phase of the feedback clock signal FDBCLK and outputs the phase comparison signal PD. After that, the delay control unit 127 outputs the delay control signal DLY_CTRL<0:n>, which corresponds to the phase comparison signal PD, to the variable delay unit 121. When such a loop is repeated so that the phase of the reference clock signal REFCLK coincides with the phase of the feedback clock signal FDBCLK, the DLL clock signal DLLCLK is finally locked. In other words, when the delay amount of the variable delay unit 121 is gradually tracked from the initial delay amount to the first delay amount through the repeated loops, the DLL clock signal DLLCLK is finally locked when the initial delay amount and the first delay amount become identical.
Accordingly, the output buffer 140 outputs the data DQ_DATA to the outside in response to the DLL clock signal DLLCLK.
According to the semiconductor device 100, the data DQ_DATA may be outputted to the outside in synchronization with the rising and falling edges of the external clock signal EXTCLK.
However, the semiconductor device 100 having the above-described configuration has the following concerns.
FIGS. 4A and 4B include timing diagrams illustrating a case in which the initial position of the feedback clock signal FDBCLK differs depending on variations of a process/voltage/temperature (PVT) condition and diagrams for explaining the process in which the first delay amount of the variable delay unit 121 is tracked according to the above-described case. FIGS. 5A and 5B are diagrams for explaining the concerns of the conventional semiconductor device in correspondence with FIGS. 4A and 4B.
When the initial position of the feedback clock signal FDBCLK is set as illustrated in FIG. 4A with respect to the reference clock signal REFCLK, the first delay amount of the variable delay unit 121 is decided through a sufficient number of loops. However, when the initial position of the feedback clock signal FDBCLK is set as illustrated in FIG. 4B with respect to the reference clock signal REFCLK, the first delay amount of the variable delay unit 121 is decided through an insufficient number of loops. In other words, in the case of FIG. 4A, a large delay amount is used to track the delay amount of the variable delay unit 121 to the first delay amount. In the case of FIG. 4B, however, a small delay amount is used to track the delay amount of the variable delay unit 121 to the first delay amount.
In this case, when the PVT condition varies, for example, the power supply voltage VDD decreases or the temperature increases after locking is completed, the first delay amount locked in the variable delay unit 121 and the second delay amount preset in the replica delay unit 123 may increase. Hereafter, for convenience of description, suppose that only the second delay amount preset in the replica delay unit 123 is affected by the variation of the PVT condition. When the second delay amount preset in the replica delay unit 123 increases, the position of the feedback clock signal FDBCLK is delayed by the increase of the second delay amount. In this case, the DLL 120 regenerates the DLL clock signal DLLCLK through a loop. More specifically, when the phase comparison unit 125 outputs the phase comparison signal PD for adjusting the distorted phase of the feedback clock DLLCLK to the phase of the reference clock signal REFCLK, and the delay control unit 127 generates the delay control signal DLY_CTRL<0:n> corresponding to the phase comparison signal PD, the variable delay unit 121 reduces the locked first delay amount. At this time, when a large delay amount is used to track the first delay amount as illustrated in FIG. 4A, the delay amount for reducing the first delay amount is sufficient as illustrated in FIG. 5A. However, when a small delay amount is used to track the first delay amount as illustrated in FIG. 4B, the delay amount for reducing the first delay amount is insufficient as illustrated in FIG. 5B. In other words, when the locked first delay amount is larger than the increase of the second delay amount based on the variation of the PVT condition, the delay amount for reducing the first delay amount becomes insufficient. Therefore, when the first delay amount required for locking was tracked by using a small delay amount, the first delay amount may not be sufficient, if the PVT condition varies after locking is completed. In this case, the delay amount required for locking may not be precisely tracked to the locking point.